In a microprocessor employing a load-store register architecture, a significant percentage of the instructions in almost any code sequence are memory access instructions, in which data must be read from or written to a main memory address indicated by the instructions. Because main memory accesses, whether involving a read or a write, are slow relative to instruction execution, cache memories are utilized to reduce memory access latency. Often, a cache memory architecture includes multiple tiers of cache memories where each tier is relatively larger, but also relatively slower, than the preceding tier.